A robust self-calibrating transmission scheme for on-chip networks
Worm, F.
Ienne, P.
Thiran, P.
De Micheli, G.
Processor Archit. Lab., Swiss Fed. Inst. of Technol. Lausanne, Switzerland;
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publication Date: Jan. 2005
Volume: 13,
Issue: 1
On page(s): 126- 139
ISSN: 1063-8210
INSPEC Accession Number: 8261440
Digital Object Identifier: 10.1109/TVLSI.2004.834241
Current Version Published: 2005-01-24
Abstract
Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. We examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements.
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