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Dynamic testing of Xilinx Virtex-II field programmable gate array (FPGA) input/output blocks (IOBs)
Swift, G.M. Rezgui, S. George, J. Carmichael, C. Napier, M. Maksymowicz, J. Moore, J. Lesea, A. Koga, R. Wrobel, T.F.
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA;

This paper appears in: Nuclear Science, IEEE Transactions on
Publication Date: Dec. 2004
Volume: 51, Issue: 6, Part 2
On page(s): 3469- 3474
ISSN: 0018-9499
INSPEC Accession Number: 8225503
Digital Object Identifier: 10.1109/TNS.2004.839190
Current Version Published: 2004-12-20

Abstract
Heavy-ion irradiation and fault injection experiments were conducted to evaluate the upset sensitivity of the Xilinx Virtex-II field programmable gate arrays (FPGAs) input/output block (IOB). Full triple module redundancy (TMR) of the IOBs, in combination with regular configuration scrubbing, proved to be a quite effective upset mitigation method.

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