A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR
Yun Chiu
Gray, P.R.
Nikolic, B.
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Dec. 2004
Volume: 39,
Issue: 12
On page(s): 2139- 2151
ISSN: 0018-9200
INSPEC Accession Number: 8202799
Digital Object Identifier: 10.1109/JSSC.2004.836232
Current Version Published: 2004-11-30
Abstract
A 1.8-V 14-b 12-MS/s pseudo-differential pipeline analog-to-digital converter (ADC) using a passive capacitor error-averaging technique and a nested CMOS gain-boosting technique is described. The converter is optimized for low-voltage low-power applications by applying an optimum stage-scaling algorithm at the architectural level and an opamp and comparator sharing technique at the circuit level. Prototyped in a 0.18-μm 6M-1P CMOS process, this converter achieves a peak signal-to-noise plus distortion ratio (SNDR) of 75.5 dB and a 103-dB spurious-free dynamic range (SFDR) without trimming, calibration, or dithering. With a 1-MHz analog input, the maximum differential nonlinearity is 0.47 LSB and the maximum integral nonlinearity is 0.54 LSB. The large analog bandwidth of the front-end sample-and-hold circuit is achieved using bootstrapped thin-oxide transistors as switches, resulting in an SFDR of 97 dB when a 40-MHz full-scale input is digitized. The ADC occupies an active area of 10 mm2 and dissipates 98 mW.
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