An industrial evaluation of DRAM tests
van de Goor, A.J.
Delft Univ. of Technol., Delft, Netherlands;
This paper appears in: Design & Test of Computers, IEEE
Publication Date: Sept.-Oct. 2004
Volume: 21,
Issue: 5
On page(s): 430- 440
ISSN: 0740-7475
INSPEC Accession Number: 8208307
Digital Object Identifier: 10.1109/MDT.2004.51
Current Version Published: 2004-10-08
Abstract
DRAM production tests are currently necessary to reach a defect-per-million level that approaches the single-digit numbers. This implies that a single memory test is insufficient; rather, a set of tests is necessary. This application of 40 well-known memory tests to 1,896 1-Mbyte × 4 DRAM chips, used up to 48 different stress combinations with each test. The results show the importance of selecting the right stress combination, and that the theoretically better tests - those covering more different functional faults - also have higher fault coverage.
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
