Hierarchical extraction and verification of symmetry constraints for analog layout automation
Sambuddha Bhattacharya
Jangkrajarng, N.
Roy Hartono
Shi, C.-J.R.
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA;
Abstract
Device matching and layout symmetry are of utmost importance to high performance analog and RF circuits. Here, we present HiLSD, the first CAD tool for the automatic detection of layout symmetry between two or more devices in a hierarchical manner. HiLSD first extracts the circuit structure from the layout, then applies an efficient pattern-matching algorithm to find all the subcircuits automatically, and finally detects layout symmetry on the portion of the layout that corresponds to extracted subcircuit instances. On a set of practical analog layouts, HiLSD is demonstrated to be much more efficient than direct symmetry detection on a flattened layout. Results from applying HiLSD to automatic analog layout retargeting for technology migration and new specifications are also described.
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