Design of FPGA interconnect for multilevel metallization
DeHon, A.
Rubin, R.
California Inst. of Technol., Pasadena, CA, USA;
This paper appears in: Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publication Date: Oct. 2004
Volume: 12,
Issue: 10
On page(s): 1038- 1050
ISSN: 1063-8210
INSPEC Accession Number: 8125406
Digital Object Identifier: 10.1109/TVLSI.2004.827562
Current Version Published: 2004-09-27
Abstract
How does multilevel metallization impact the design of field-programmable gate arrays (FPGA) interconnect? The availability of a growing number of metal layers presents the opportunity to use wiring in the third dimension to reduce area and switch requirements. Unfortunately, traditional FPGA wiring schemes are not designed to exploit these additional metal layers. We introduce an alternate topology, based on Leighton's mesh-of-trees (MoT), which carefully exploits hierarchy to allow additional metal layers to support arbitrary device scaling. When wiring layers grow sufficiently fast with aggregate network size (N), our network requires only O(N) area; this is in stark contrast to traditional, Manhattan FPGA routing schemes where switching requirements alone grow superlinearly in N. In practice, we show that, even for the admittedly small designs in the Toronto "FPGA Place and Route Challenge," arity-4 MoT networks require 26% fewer switches than the standard, Manhattan FPGA routing scheme.
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