Scaling to the end of silicon with EDGE architectures
Burger, D.
Keckler, S.W.
McKinley, K.S.
Dahlin, M.
John, L.K.
Lin, C.
Moore, C.R.
Burrill, J.
McDonald, R.G.
Yoder, W.
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA;
This paper appears in: Computer
Publication Date: July 2004
Volume: 37,
Issue: 7
On page(s): 44- 55
ISSN: 0018-9162
INSPEC Accession Number: 8033460
Digital Object Identifier: 10.1109/MC.2004.65
Current Version Published: 2004-07-12
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Microprocessor designs are on the verge of a post-RISC era in which companies must introduce new ISAs to address the challenges that modern CMOS technologies pose while also exploiting the massive levels of integration now possible. To meet these challenges, we have developed a new class of ISAs, called explicit data graph execution (EDGE), that will match the characteristics of semiconductor technology over the next decade. The TRIPS architecture is the first instantiation of an EDGE instruction set, a new, post-RISC class of instruction set architectures intended to match semiconductor technology evolution over the next decade, scaling to new levels of power efficiency and high performance.
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