A 12-bit 75-MS/s pipelined ADC using open-loop residue amplification
Murmann, B.
Boser, B.E.
Berkeley Sensor & Actuator Center, Univ. of California, Berkeley, CA, USA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Dec. 2003
Volume: 38,
Issue: 12
On page(s): 2040- 2050
ISSN: 0018-9200
INSPEC Accession Number: 7887510
Digital Object Identifier: 10.1109/JSSC.2003.819167
Current Version Published: 2004-01-08
Abstract
Precision amplifiers dominate the power dissipation in most high-speed pipelined analog-to-digital converters (ADCs). We propose a digital background calibration technique as an enabling element to replace precision amplifiers by simple power-efficient open-loop stages. In the multibit first stage of a 12-bit 75-MSamples/s proof-of-concept prototype, we achieve more than 60% residue amplifier power savings over a conventional implementation. The ADC has been fabricated in a 0.35-μm double-poly quadruple-metal CMOS technology and achieves typical differential and integral nonlinearity within 0.5 LSB and 0.9 LSB, respectively. At Nyquist input frequencies, the measured signal-to-noise ratio is 67 dB and the total harmonic distortion is -74 dB. The IC consumes 290 mW at 3 V and occupies 7.9 mm2.
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