Exploring regular fabrics to optimize the performance-cost trade-off
Pileggi, L.
Schmit, H.
Strojwas, A.J.
Gopalakrishnan, P.
Kheterpal, V.
Koorapaty, A.
Patel, C.
Rovner, V.
Tong, K.Y.
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA;
This paper appears in: Design Automation Conference, 2003. Proceedings
Publication Date: 2-6 June 2003
On page(s): 782- 787
ISBN: 1-58113-688-9
INSPEC Accession Number: 7853037
Current Version Published: 2003-08-11
Abstract
While advances in semiconductor technologies have pushed achievable scale and performance to phenomenal limits for ICs, nanoscale physical realities dictate IC production based on what we can afford. We believe that IC design and manufacturing can be made more affordable, and reliable, by removing some design and implementation flexibility and enforcing new forms of design regularity. This paper discusses some of the trade-offs to consider for determination of how much regularity a particular IC or application can afford. A Via Patterned Gate Array is proposed as one such example that trades performance for cost by way of new forms of design regularity.
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