Process integration of single-wafer technology in a 300-mm fab, realizing drastic cycle time reduction with high yield and excellent reliability
Ikeda, S.
Nemoto, K.
Funabashi, M.
Uchino, T.
Yamamoto, H.
Yabuoshi, N.
Sasaki, Y.
Komori, K.
Suzuki, N.
Nishihara, S.
Sasabe, S.
Koike, A.
Trecenti-Technol. Inc., Ibaraki, Japan;
This paper appears in: Semiconductor Manufacturing, IEEE Transactions on
Publication Date: May 2003
Volume: 16,
Issue: 2
On page(s): 102- 110
ISSN: 0894-6507
INSPEC Accession Number: 7633532
Digital Object Identifier: 10.1109/TSM.2003.810935
Current Version Published: 2003-05-13
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In this paper, we discuss a new technology implemented with single-wafer processing for a 300-mm fab. Newly developed equipment and chemicals reduce the process time and provide cost savings. The combination of fully automated systems and single-wafer processing significantly reduces queuing time. The process has been re-integrated to eliminate long time processes and make it suitable for single-wafer technologies. As a result, a very aggressive cycle time (0.25 days/layer) with high yield, in double-polysilicon, sextuple-metal, 0.18-μm logic process has been demonstrated. High-performance devices with excellent reliability are also obtained. A new methodology for detecting parametric errors effectively in the early stages of production is implemented for quick yield ramp up.
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