A 70 ns high density 64K CMOS dynamic RAM
Chwang, R.J.C.
Choi, M.
Creek, D.
Stern, S.
Pelley, P.H.
Schutz, J.D.
Warkentin, P.A.
Bohr, M.T.
Yu, K.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Oct 1983
Volume: 18,
Issue: 5
On page(s): 457- 463
ISSN: 0018-9200
Current Version Published: 2003-01-06
Abstract
A 64K × 1 CMOS dynamic RAM has been developed in a double-poly n-well CMOS technology with device scaling to the HMOS III level. A p-channel memory array with n-well protection reduced the operating soft error rate to less than one FIT. Periphery complexity is simplified due to CMOS circuits resulting in a size of 30,464 mil/SUP 2/ with a redundancy efficiency of 68%. The RAM has a typical access time of 70 ns and a CMOS standby power of 25 μW. In addition, a static column design offers 35-ns data cycle time for high-bandwidth application.
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