Using formal specifications for functional validation of hardwaredesigns
Shimizu, K.
Dill, D.L.
Stanford Univ., CA;
This paper appears in: Design & Test of Computers, IEEE
Publication Date: Jul/Aug 2002
Volume: 19,
Issue: 4
On page(s): 96-106
ISSN: 0740-7475
References Cited: 6
CODEN: IDTCEC
INSPEC Accession Number: 7331634
Digital Object Identifier: 10.1109/MDT.2002.1018138
Current Version Published: 2002-08-07
Abstract
Formal specifications can help resolve both ambiguity issues and
correctness problems in verifying complex hardware designs. This new
methodology shows how specifications can also help design productivity
by automating many procedures that are now done manually. Input
sequences, output assertions, and a simulation coverage metric for the
design under verification are all generated directly from the
specification
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