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A single-chip, 1.6-billion, 16-b MAC/s multiprocessor DSP

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16 Author(s)
B. Ackland ; Bell Labs., Lucent Technol., Holmdel, NJ, USA ; A. Anesko ; D. Brinthaupt ; S. J. Daubert
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An MIMD multiprocessor digital signal-processing (DSP) chip containing four 64-b processing elements (PE's) interconnected by a 128-b pipelined split transaction bus (STBus) is presented. Each PE contains a 32-b RISC core with DSP enhancements and a 64-b single-instruction, multiple-data vector coprocessor with four 16-b MAC/s and a vector reduction unit. PEs are connected to the STBus through reconfigurable dual-ported snooping L1 cache memories that support shared memory multiprocessing using a modified-MESI data coherency protocol. High-bandwidth data transfers between system memory and on-chip caches are managed in a pipelined memory controller that supports multiple outstanding transactions. An embedded RTOS dynamically schedules multiple tasks onto the PEs. Process synchronization is achieved using cached semaphores. The 200-mm/sup 2/, 0.25-/spl mu/m CMOS chip operates at 100 MHz and dissipates 4 W from a 3.3-V supply.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:35 ,  Issue: 3 )