Referenced Items are not available for this document.
In this paper, we have proposed a fast and easy-to-develop FPGA-based fault injection technique. This technique uses the Altera FPGAs debugging facilities in order to inject SEU fault model in both flip-flops and memory units. Since this method uses the FPGAs built-in facilities, it imposes a negligible performance and area overhead on the system. The experimental results on Leon2 processor shows that the proposed technique is on average four orders of magnitude faster than a simulation-based fault injection.
Published in:
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Date of Conference: 12-16 March 2012
- Page(s):
- 586 - 589
- ISSN :
- 1530-1591
- Print ISBN:
- 978-1-4577-2145-8
- INSPEC Accession Number:
- 12656785
- Conference Location :
- Dresden
- Digital Object Identifier :
- 10.1109/DATE.2012.6176538
- Product Type:
- Conference Publications
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