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Enhancing online error detection through area-efficient multi-site implications

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5 Author(s)
N. Alves ; School of Engineering, Brown University, Providence, RI 02906, USA ; Y. Shi ; J. Dworak ; R. I. Bahar
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We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic.

Published in:

29th VLSI Test Symposium

Date of Conference:

1-5 May 2011