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Browse Conference Publications > 3D System Integration, 2009. ... Help

Electrical modeling of Through Silicon and Package Vias

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5 Author(s)
Bandyopadhyay, T. ; Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA ; Chatterjee, R. ; Daehyun Chung ; Swaminathan, M.
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This paper presents analytical modeling and 3D full-wave electromagnetic (EM) simulation of the bias voltage dependent semiconductor (MOS) capacitance of a Through Silicon Via (TSV). An accurate electrical model of the TSV is proposed by considering the semiconductor effects. The high-frequency electrical performance of TSVs and Through-Package Vias (TPVs) are compared by means of 3D EM simulations. A parametric study is performed on TSV capacitance and design guidelines are presented for signal and power TSVs.

Published in:
3D System Integration, 2009. 3DIC 2009. IEEE International Conference on

Date of Conference: 28-30 Sept. 2009

Page(s):
1 - 8
E-ISBN :
978-1-4244-4512-7
Print ISBN:
978-1-4244-4511-0
INSPEC Accession Number:
10951266
Conference Location :
San Francisco, CA
Digital Object Identifier :
10.1109/3DIC.2009.5306542
Product Type:
Conference Publications

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