A 107.4 dB SNR Multi-Bit Sigma Delta ADC With 1-PPM THD at $-$0.12 dB From Full Scale Input
Wu, J.-Y.
Zhang, Z.
Subramoniam, R.
Maloberti, F.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 3060-3066
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2032753
Current Version Published: 2009-11-03
Abstract A second order sigma delta modulator (SDM) with a 5-bit quantizer has been presented using several novel techniques: simplified DAC arrays for easy implementation, high-order truncation noise shaping for increased tolerance to analog imperfections, and an extended dynamic range for a maximum input signal swing of up to $-0.12 ~{hbox {dB}}_{rm FS}$ (Full Scale). With truncation filters and a pseudo SDM in the DSP, the truncation and saturation errors are compensated through the DAC arrays and the DSP. The design, fabricated in a 0.18 $mu{hbox {m}}$ dual gate oxide (DGO) process obtains a signal-to-noise-and–distortion ratio (SNDR) of 105.9 dB and a dynamic range (DR) of 107.4 dB with 31.25-KHz bandwidth at an 8-MHz sampling frequency and a power consumption of 14.7 mW.
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