A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops
Zhang, L.
Yu, X.
Sun, Y.
Rhee, W.
Wang, D.
Wang, Z.
Chen, H.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 2922-2934
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2028927
Current Version Published: 2009-11-03
Abstract A finite-modulo fractional-$N$ PLL utilizing a low-bit high-order $DeltaSigma$ modulator is presented. A 4-bit fourth-order $DeltaSigma$ modulator not only performs non-dithered 16-modulo fractional-$N$ operation but also offers less spur generation with negligible quantization noise. Further spur reduction is achieved by charge compensation in the voltage domain and phase interpolation in the time domain, which significantly relaxes the dynamic range requirement of the charge pump compensation current. A 1.8–2.6 GHz fractional-$N$ PLL is implemented in 0.18 $mu{hbox {m}}$ CMOS. By employing high-order deterministic $DeltaSigma$ modulation and hybrid spur compensation, the spur level of less than $-$55 dBc is achieved when the ratio of the bandwidth to minimum frequency resolution is set to 1/4. The prototype PLL consumes 35.3 mW in which only 2.7 mW is consumed by the digital modulator and compensation circuits.
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