A 1.25–5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS
Toifl, T.
Menolfi, C.
Buchmann, P.
Kossel, M.
Morf, T.
Schmatz, M. L.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 2901-2910
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2028919
Current Version Published: 2009-11-03
Abstract A clock generator for high-speed chip-to-chip link receivers was implemented in a 45-nm CMOS SOI technology. A low sensitivity to supply voltage noise was achieved by means of a low-dropout voltage regulator using a replica feedback in the regulation loop, where the replica resistance is regulated by a second loop. We show that by adjusting the replica load the necessary matching of the $gm/gds$ ratio of the current sources can be achieved. A power supply rejection of $>,$22 dB was measured up to 1 GHz for a circuit operating from a 1 V supply with 80$~$pF decoupling capacitance and a load current of 18.5 mA. The maximum supply sensitivity of the clock generation circuit (DLL plus phase rotators) was 4.5 ps/100 mV supply noise over the entire noise frequency range at clock frequencies from 1.25–5 GHz. The phase rotator achieves a wide range of operating frequencies by providing programmable rise/fall times in its selection stage. In addition, low voltage operation of the circuit was demonstrated at supply voltages down to 0.7$~$V and a clock frequency of 1.6 GHz.
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