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BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel
Jang, Y.-C. Chung, H. Choi, Y. Park, H. Kim, J. Lim, S. Sunwoo, J. Park, M.-S. Kim, H.-S. Kim, S.-Y. Lee, Y.-S. Kim, W.-S. Lee, J.-B. Yoo, J. Kim, C.

This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44, Issue: 11
On page(s): 2987-2998
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2028948
Current Version Published: 2009-11-03

Abstract
A 1-Gbit DRAM with 5.8-Gb/s/pin unidirectional differential I/Os was implemented by 70 nm DRAM process and a main memory module with dual in-line memory module was assembled. The implemented DRAM chips have control methods for core noise injection and a cyclic redundancy check (CRC) generator for outer-data inner-command architecture. Measurements for bit error rate and jitter performance of the transmitter was performed on an electrical test board which emulates the real memory system's environment. Also, the effect on power noise was analyzed from the DRAM chips with three class values of power decoupling capacitance for the peripheral part. The results show that no additional coding for the differential I/O protection in DRAM, like CRC, is required up to 5.8-Gb/s/pin operation.

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