A 2.4 GHz Low-Power Sixth-Order RF Bandpass $DeltaSigma$ Converter in CMOS
Ryckaert, J.
Borremans, J.
Verbruggen, B.
Bos, L.
Armiento, C.
Craninckx, J.
Van der Plas, G.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 2873-2880
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2028914
Current Version Published: 2009-11-03
Abstract A sixth-order RF bandpass $DeltaSigma$ ADC operating on the 2.4 GHz ISM band, which is suitable for RF digitization is presented. The bandpass loop filter is based on digitally programmable $Gm$–$LC$ resonators that can be calibrated online to adjust the RF center frequency. By sampling below the input Nyquist frequency, the clock in the system was reduced to 3$~$GHz, allowing a large reduction of the power consumption. Implemented in a standard 90 nm CMOS process, the IC achieves 40$~$dB and 62 dB of SNDR and SFDR, respectively, on a 60 MHz bandwidth with 40 mW of power consumption leading to a FoM of 245 GHz/W (4.1 pJ/conversion step). This implementation paves a possible way towards direct RF digitization receiver architectures.
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
