Large-Scale SRAM Variability Characterization in 45 nm CMOS
Guo, Z.
Carlson, A.
Pang, L.-T.
Duong, K. T.
Liu, T.-J. K.
Nikolic, B.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 3174-3192
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2032698
Current Version Published: 2009-11-03
Abstract Increased process variability presents a major challenge for future SRAM scaling. Fast and accurate validation of SRAM read stability and writeability margins is crucial for estimating yield in large SRAM arrays. Conventional SRAM read/write metrics are characterized through test structures that are able to provide limited hardware measurement data and cannot be used to investigate cell bit fails in functional SRAM arrays. This work presents a method for large-scale characterization of read stability and writeability in functional SRAM arrays using direct bit-line measurements. A test chip is implemented in a 45 nm CMOS process. Large-scale SRAM read/write metrics are measured and compared against conventional SRAM stability metrics. Results show excellent correlation to conventional SRAM read/write metrics as well as ${rm V}_{rm MIN}$ measurements near failure.
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