A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method
Mantyniemi, A.
Rahkonen, T.
Kostamovaara, J.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 3067-3078
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2032260
Current Version Published: 2009-11-03
Abstract This paper describes a time-to-digital converter (TDC) with $sim $1.2 ps resolution and $sim $327 $mu$s dynamic range suitable for laser range-finding application for example. The resolution of $sim $1.2 ps is achieved with interpolation based on a cyclic time domain successive approximation (CTDSA) method that resolves the time difference between two non-repetitive signals using binary search. The method utilizes a pair of digital-to-time converters (DTC), the propagation delay difference between which is implemented by digitally controlling the unit load capacitors of their delay cells, thus enabling sub-gate delay timing resolution. The rms single-shot precision, i.e., standard deviation $sigma $-value of the TDC is 3.2 ps, which is achieved by using an external integral nonlinearity look-up table (INL-LUT) for the interpolators. The power consumption is 33 mW at 100 MHz with a 3.3 V operating voltage. The prototypes were fabricated in a 0.35 $mu{hbox {m}}$ CMOS process.
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