An 8$,times,$5 Gb/s Parallel Receiver With Collaborative Timing Recovery
Agrawal, A.
Liu, A.
Hanumolu, P. K.
Wei, G.-Y.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 3120-3130
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2033399
Current Version Published: 2009-11-03
Abstract This paper presents the design of an 8 channel, 5$~$Gb/s per channel parallel receiver with collaborative timing recovery and no forwarded clock. The receiver architecture exploits synchrony in the transmitted data streams in a parallel interface and combines error information from multiple phase detectors in the receiver to produce one global synthesized clock. This collaborative timing recovery scheme enables wideband jitter tracking without increasing the dithering jitter in the synthesized clock. Circuit design techniques employed to implement this receiver architecture are discussed. Experimental results from a 130 nm CMOS test chip demonstrate the enhanced tracking bandwidth and lower dithering jitter of the recovered clock.
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
