A 10-Bit 500-MS/s 55-mW CMOS ADC
Verma, A.
Razavi, B.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 3039-3050
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2031044
Current Version Published: 2009-11-03
Abstract A pipelined ADC incorporates a digital foreground calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a high-speed, low-power op amp topology and an accurate on-chip resistor ladder and designed in 90-nm CMOS technology, the ADC achieves a DNL of 0.4 LSB and an INL of 1 LSB. The prototype digitizes a 233-MHz input with 53-dB SNDR while consuming 55$~$mW from a 1.2-V supply.
Index
Terms
Available to subscribers and IEEE members.
References
Available to subscribers and IEEE members.
Citing Documents
Available to subscribers and IEEE members.
Cart
