ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier
Paul, B. C.
Fujita, S.
Okajima, M.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 2935-2942
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2028928
Current Version Published: 2009-11-03
Abstract We present a ROM-based 16$,times,$16 multiplier for low-power applications. The design uses sixteen 4$,times,$4 ROM-based multiplier blocks followed by carry-save adders and a final carry-select adder (all ROM-based) to obtain the 32 bit output. All ROM blocks are implemented using single transistor ROM cells and eliminating identical rows and columns for optimizing the power and performance. Measurement results in 0.18 $mu$m CMOS process show a 40% reduction in power over the conventional carry-save array multiplier when operated at its maximum frequency. The ROM-based design also provides 44% less delay than the array multiplier with a minimal increase (7.7%) in power. This demonstrates the low-power operation of the ROM-based multiplier also at higher frequencies.
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