A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control
Jung, H.-K.
Lee, K.
Kim, J.-S.
Lee, J.-J.
Sim, J.-Y.
Park, H.-J.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 2891-2900
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2028917
Current Version Published: 2009-11-03
Abstract By using the data timing control at the transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 3-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). The difference in propagation velocity with the signal modes (odd, static, even) is compensated for by sending data earlier or later at TX according to the signal modes, so that the signals of different modes arrive at receiver at the same time. The proposed TX was implemented by using a 0.18 $mu{hbox {m}}$ CMOS process. The measurement shows that the proposed TX reduces the RX jitters by about 30 ps (more than 50% of the added jitter due to CIJ and ISI) at the data rates from 2.6 Gb/s to 4.0 Gb/s. The proposed scheme can be applied to more than three parallel microstrip lines.
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