A World-Band Triple-Mode 802.11a/b/g SOC in 130-nm CMOS
Lai, J.-W.
Wu, C.-H.
Lin, A.
Hong, W.-H.
Wang, C.-Y.
Shen, C.-H.
Lin, Y.-H.
Cho, Y.-H.
Chen, Y.-C.
Chung, Y.-H.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 2911-2921
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2028920
Current Version Published: 2009-11-03
Abstract A fully integrated system-on-a-chip (SOC) in 130-nm CMOS technology compliant with world-band 802.11a/b/g is presented. This SOC integrates all blocks including 2.4-GHz/5-GHz RF tranceiver, baseband physical layer (PHY), and the medium access controller (MAC). At 1.8 V, the whole SOC dissipates 144/168 mA in receiving mode and 114/150 mA in transmitting mode for 2.4-GHz/5-GHz-band operations. The measured receiver sensitivity at 2.4 GHz/5 GHz is $-{hbox{77.5}}/-{hbox{74}} hbox{dBm}$ at 54 Mb/s rate, and the transmitter EVM at 54 Mb/s rate is $-{hbox{33}}/-{hbox{30}} {hbox {dB}}$ at an output power of $-{hbox{7}}/-{hbox{8}} hbox{dBm}$. By integrating multiple on-chip LDOs with no off-chip capacitors, this SOC features the capability of being directly supplied by off-chip switching-type DC/DC converter without performance degradation.
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