Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture
Ohhata, K.
Uchino, K.
Shimizu, Y.
Oyama, K.
Yamashita, K.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 2881-2890
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2028915
Current Version Published: 2009-11-03
Abstract This paper describes a high-speed, low-power CMOS subranging analog-to-digital converter (ADC). A reference voltage precharging architecture and the introduction of a comparator with a built-in threshold voltage in the fine ADC are proposed to reduce the settling time of the reference voltage. A T/H circuit with a body-bias control circuit is employed to reduce distortion at a high sampling rate. Moreover, a $V_{rm TH}$ generator using a replica of the original comparator is also proposed to compensate for $V_{rm TH}$ deviation due to the process variations. A test chip was fabricated using 90-nm CMOS technology, and showed a high-sampling rate of 770 MS/s and a low-power consumption of 70 mW.
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