This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Nov. 2009
Volume: 44,
Issue: 11
On page(s): 3111-3119
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2009.2031577
Current Version Published: 2009-11-03
Abstract An all-digital spread-spectrum clock generator (SSCG) has been fabricated in a 0.18 $mu{hbox {m}}$ CMOS process. The analysis and design of this all-digital SSCG is presented. A mixed-signal phase and frequency detector is adopted to reduce the jitter, eliminate a digital adder, and also reduce latency. A Vernier time-to-digital converter (TDC) with time amplifiers is realized to enhance the timing resolution of the TDC and to track the frequency modulation in the SSCG. A digitally controlled oscillator with a resolution enhancement circuit is also presented. The measured electromagnetic interference reduction is 10.48 dB. The measured peak-to-peak jitter and rms jitter are 28.4 ps and 4$~$ps, respectively, at 1.5 GHz.
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