High-Speed Optical Receivers With Integrated Photodiode in 130 nm CMOS
Tavernier, F.
Steyaert, M.S.J.
Dept. Elektrotechniek, Katholieke Univ. Leuven, Heverlee, Belgium;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Oct. 2009
Volume: 44,
Issue: 10
On page(s): 2856-2867
ISSN: 0018-9200
INSPEC Accession Number: 10880530
Digital Object Identifier: 10.1109/JSSC.2009.2028755
Current Version Published: 2009-09-22
Abstract
The design and measurement of two optical receivers with integrated photodiode in 130 nm CMOS is presented. The low bandwidth, which is typical for photodiodes in CMOS technologies, is circumvented by a differential photodiode topology on the one hand and by including an optimized equalizer in the receiver chain on the other hand. The low responsivity of a CMOS photodiode is compensated by a very low-noise design for the differential TIA. The disadvantage of such a low-noise design is its high power consumption. Therefore, a design strategy is presented where part of the circuit is biased in weak inversion. Doing so, the power consumption is decreased from 138 mW for the standard design to only 74.16 mW. Both designs are measured optically with 850 nm modulated light and are able to operate at 4.5 Gbit/s with a BER lower than 10-12. The sensitivities for this BER and speed are - 3.8 dBm and -3.4 dBm respectively. The receivers even work up to 5 Gbit/s for BER values around 10-9.
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