A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC
Jongwoo Lee
Kang, J.
Sunghyun Park
Jae-sun Seo
Anders, J.
Guilherme, J.
Flynn, M.P.
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Oct. 2009
Volume: 44,
Issue: 10
On page(s): 2755-2765
ISSN: 0018-9200
INSPEC Accession Number: 10880525
Digital Object Identifier: 10.1109/JSSC.2009.2028052
Current Version Published: 2009-09-22
Abstract
A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.
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