Resilient Self-V$_{rm DD}$-Tuning Scheme With Speed-Margining for Low-Power SRAM
Ya-Chun Lai
Shi-Yu Huang
Hsuan-Jung Hsu
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Oct. 2009
Volume: 44,
Issue: 10
On page(s): 2817-2823
ISSN: 0018-9200
INSPEC Accession Number: 10880519
Digital Object Identifier: 10.1109/JSSC.2009.2027543
Current Version Published: 2009-09-22
Abstract
Lowering the supply voltage is an effective way to significantly reduce the power consumption of a static random access memory (SRAM). However, the minimum supply voltage (Vminf) required to support a given operating frequency in an SRAM macro is often elusive from one chip to another due to process variations. Moreover, temperature could vary when an SRAM macro is in operation, and thus exacerbating the problem since temperature variation could affect the Vminf . In this paper, we propose an on-chip self-VDD-tuning scheme that automatically adjusts each manufactured SRAM macro to a minimal voltage near its Vminf. Our scheme can provide a user-specified speed margin (e.g., 10% of the target frequency), and thereby creating a guard band for assuring robust operations over a wide range of temperatures. Simulation results show that, with the proposed speed margining technique, a 64 Kb SRAM macro can tolerate temperature up to 125degC. Measurement results from a test chip in a 0.18-mum CMOS process also demonstrate that we can achieve 40% power savings for an 8 Kb SRAM macro operating at 150 MHz by means of this resilient self-VDD-tuning.
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