A High-Frequency Clock Distribution Network Using Inductively Loaded Standing-Wave Oscillators
Sasaki, M.
Hiroshima Univ., Higashi-Hiroshima, Japan;
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: Oct. 2009
Volume: 44,
Issue: 10
On page(s): 2800-2807
ISSN: 0018-9200
INSPEC Accession Number: 10880514
Digital Object Identifier: 10.1109/JSSC.2009.2027541
Current Version Published: 2009-09-22
Abstract
The present paper introduces a resonant clock generation and distribution scheme that uses uniform amplitude and uniform phase standing wave oscillators in order to distribute a high-frequency clock signal with low skew, low jitter, and low power. A suitable distributed resonator for a global clock distribution that is inductively loaded transmission line generating a uniform amplitude and uniform phase standing wave is realized through detailed analysis of a standing wave on a loaded transmission line. A test chip is fabricated using 0.18-mum 6 M CMOS technology, and a cascaded distribution network is implemented for a global clock distribution with a space-filling curve. Furthermore, distributed local LC tanks are implemented as local resonant clock networks, which are composed of parasitic capacitors and small spiral inductors. The distributed local LC tanks are driven by a fine clock distributed with cascaded standing-wave oscillators and reduce the primary power in the clock distribution, which is dissipated as dynamic power in the parasitic capacitance of latches and/or flip flops. The measurement results reveal that, at 9.4 GHz, the peak-to-peak jitter is 5.2 ps and the clock skew is 0.8 ps, and the global and local distributions dissipated only 17% and 23% of CV2f power, respectively.
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