Searching for the dream embedded memory
Natarajan, S.
Chung, S.
Paris, L.
Keshavarzi, A.
TSMC, Taiwan;
This paper appears in: Solid-State Circuits Magazine, IEEE
Publication Date: Summer 2009
Volume: 1,
Issue: 3
On page(s): 34-44
ISSN: 1943-0582
INSPEC Accession Number: 10824914
Digital Object Identifier: 10.1109/MSSC.2009.933521
Current Version Published: 2009-08-07
Abstract
In this paper, it was concluded that embedding memories into an SOC increases bandwidth, speed, and reliability of the overall system, while reducing power consumption and form factor. Embedded DRAM is an attractive choice for embedded memory because it consumes only 30% of standby power and 10% of active power, while it occupies only 30% of the area, compared to SRAM at the 90-nm CMOS node. At the same level of technology, embedded DRAM can achieve a soft-error rate of less than 1 FIT per Mb, which is ten to 1,000 times smaller than that of a comparable SRAM. However, a careful assessment of the benefits must be weighed against the increased process cost of four to six extra masks and masking operations. Emerging memories such as MRAM and PCRAM are nonvolatile with almost unlimited endurance and offer five orders of magnitude faster write speed than flash memory does, yet with read speed close to that of embedded DRAM. In addition, they are potentially simpler to fabricate. The MRAM cell is based on a multilayer magnetic tunnel junction with a parallel or antiparallel state to provide a 0 or1 logic state. The PCRAM cell is based on a reversible phase change between crystalline and amorphous states to provide a 0 or 1 state. These mechanisms have been proven in magnetic heads in hard disk drives and in readable/writable DVDs in discrete form. They are suitable for use as level-two or level-three cache or main memory or as storage devices for code or data. These emerging memories are about ready to be integrated into mainstream CMOS semiconductor processes.
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