Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing
Xiaoheng Chen
Jingyu Kang
Shu Lin
Akella, V.
Dept. of Electr. & Comput. Eng., Univ. of California, Davis, CA;
Abstract
FPGAs are widely used for evaluating the error-floor performance of LDPC (low-density parity check) codes. We propose a scalable vector decoder for FPGA-based implementation of quasi-cyclic (QC) LDPC codes that takes advantage of the high bandwidth of the embedded memory blocks (called Block RAMs in a Xilinx FPGA) by packing multiple messages into the same word. We describe a vectorized overlapped message passing algorithm that results in 3.5times to 5.5times speedup over state-of-the-art FPGA implementations in literature.
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