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Design optimizations to improve placeability of partial reconfiguration modules
Koester, M.   Luk, W.   Hagemeyer, J.   Porrmann, M.  
Dept. of Comput., Imperial Coll. London, London;

This paper appears in: Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Publication Date: 20-24 April 2009
On page(s): 976-981
Location: Nice,
ISSN: 1530-1591
ISBN: 978-1-4244-3781-8
INSPEC Accession Number: 10730295
Current Version Published: 2009-06-23

Abstract
In partially reconfigurable architectures, system components can be dynamically loaded and unloaded allowing resources to be shared over time. This paper focuses on the relation between the design options of partial reconfiguration modules and their placement at run-time. For a set of dynamic system components, we propose a design method that optimizes the feasible positions of the resulting partial reconfiguration modules to minimize position overlaps. We introduce the concept of subregions, which guarantees the parallel execution of a certain number of partial reconfiguration modules for tiled reconfigurable systems. Experimental results, which are based on a Xilinx Virtex-4 implementation, show that at run-time the average number of available positions can be increased up to 6.4 times and the number of placement violations can be reduced up to 60.6%.

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