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A hybrid packet-circuit switched on-chip network based on SDM
Modarressi, M.   Sarbazi-Azad, H.   Arjomand, M.  
Comput. Eng. Dept., Sharif Univ. of Technol., Tehran;

This paper appears in: Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09.
Publication Date: 20-24 April 2009
On page(s): 566-569
Location: Nice,
ISSN: 1530-1591
ISBN: 978-1-4244-3781-8
INSPEC Accession Number: 10730482
Current Version Published: 2009-06-23

Abstract
In this paper, we propose a novel on-chip communication scheme by dividing the resources of a traditional packet-switched network-on-chip between a packet-switched and a circuit-switched sub-network. The former directs packets according to the traditional packet-switching mechanism, while the latter forwards packets over circuits which are directly established between two non-adjacent nodes by bypassing the intermediate routers. A packet may switch between the sub-networks several times to reach its destination. The circuits are set up using a low-latency and low-cost setup-network. The network resources are split between the two sub-networks using Spatial-Division Multiplexing (SDM). The work aims to improve the power and performance metrics of Network-on-Chip (NoC) architectures and benefits from the power and scalability advantage of packet-switched NoCs and superior communication performance of circuit-switching. The evaluation results show a significant reduction in power and latency over a traditional packet-switched NoC.

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