TRAM: A tool for Temperature and Reliability Aware Memory Design
Khajeh, A.
Gupta, A.
Dutt, N.
Kurdahi, F.
Eltawil, A.
Khouri, K.
Abadir, M.
Univ. of California, Irvine, CA;
Abstract
Memories are increasingly dominating Systems on Chip (SoC) designs and thus contribute a large percentage of the total system's power dissipation, area and reliability. In this paper, we present a tool which captures the effects of supply voltage Vdd and temperature on memory performance and their interrelationships. We propose a Temperature- and Reliability- Aware Memory Design (TRAM) approach which allows designers to examine the effects of frequency, supply voltage, power dissipation, and temperature on reliability in a mutually interrelated manner. Our experimental results indicate that thermal unaware estimation of probability of error can be off by at least two orders of magnitude and up to five orders of magnitude from the realistic, temperature-aware cases. We also observed that thermal aware Vdd selection using TRAM can reduce the total power dissipation by up to 2.5times while attaining an identical predefined limit on errors.
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