Comparison of Three Single-Phase PLL Algorithms for UPS Applications
Santos Filho, R. M.
Seixas, P. F.
Cortizo, P. C.
Torres, L. A. B.
Souza, A. F.
This paper appears in: Industrial Electronics, IEEE Transactions on
Publication Date: Aug. 2008
Volume: 55,
Issue: 8
On page(s): 2923-2932
ISSN: 0278-0046
Digital Object Identifier: 10.1109/TIE.2008.924205
First Published: 2008-04-25
Current Version Published: 2008-08-01
Abstract In this paper, the performance assessment of three software single-phase phase-locked loop (PLL) algorithms is carried out by means of dynamic analysis and experimental results. Several line disturbances such as phase-angle jump, voltage sag, frequency step, and harmonics are generated by a DSP together with a D/A converter and applied to each PLL. The actual minus the estimated phase-angle values are displayed, providing a refined method for performance evaluation and comparison. Guidelines for parameters adjustments are also presented. In addition, practical implementation issues such as computational delay effects, ride-through, and computational load are addressed. The developed models proved to accurately represent the PLLs under real test conditions.
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