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A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)
Hamada, N. Shiga, Y. Saito, H. Yoneda, T. Myers, C. Nanya, T.
Aizu Univ., Aizuwakamatsu;

This paper appears in: Application of Concurrency to System Design, 2008. ACSD 2008. 8th International Conference on
Publication Date: 23-27 June 2008
On page(s): 50-55
Location: Xian,
ISSN: 1550-4808
ISBN: 978-1-4244-1838-1
INSPEC Accession Number: 10221099
Digital Object Identifier: 10.1109/ACSD.2008.4574595
Current Version Published: 2008-09-19

Abstract
This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a restricted C language. Finally, this paper evaluates our method for several benchmarks through a tool implementation.

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