Implementing Legacy-C Algorithms in FPGA Co-Processors for Performance Accelerated Smart Payloads
Pingree, P.J.
Scharenbroich, L.J.
Werne, T.A.
Hartzell, C.
Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA;
This paper appears in: Aerospace Conference, 2008 IEEE
Publication Date: 1-8 March 2008
On page(s): 1-8
Location: Big Sky, MT,
ISSN: 1095-323X
ISBN: 978-1-4244-1487-1
INSPEC Accession Number: 9980099
Digital Object Identifier: 10.1109/AERO.2008.4526522
Current Version Published: 2008-05-20
Abstract
Accurate, on-board classification of instrument data is used to increase science return by autonomously identifying regions of interest for priority transmission or generating summary products to conserve transmission bandwidth. Due to on-board processing constraints, such classification has been limited to using the simplest functions on a small subset of the full instrument data. FPGA co-processor designs for SWM classifiers will lead to significant improvement in on-board classification capability and accuracy. We implemented a SWIL classifier, developed for the Hyperion instrument on the EO-1 spacecraft, on the Xilinx Virtex-4FX60 FPGA as a baseline challenge. We have taken advantage of Impulse Ctrade, the commercially available C-to- HDL tool by Impulse Accelerated Technologies, which supports the development of highly parallel, co-designed hardware algorithms (from software) and applications. This paper describes our approach for implementing the Hyperion linear SVM on the Virtex-4FX FPGA, as well as additional experiments with increased numbers of data bands and a more sophisticated SVM kernel to show the potential for better on-board classification achieved with embedded FPGAs over current in-flight capabilities.
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