Abstract
Reconfigurable hardware (RH) is used in an increasing variety of applications, many of which require support for features commonly found in general purpose systems. In this work we examine some of the challenges faced in integrating RH with general purpose processors and memory systems. We propose a new CPU-RH-memory interface that takes advantage of on-chip caches and uses virtual memory for communication. Additionally we describe the simulator model we developed to evaluate this new architecture. This work shows that an efficient interface can greatly accelerate RH applications, and provides a strong first step toward multiprocessor reconfigurable computing.
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