Optimistic Parallelization of Floating-Point Accumulation
Kapre, N.
DeHon, A.
California Inst. of Technol., Pasadena;
This paper appears in: Computer Arithmetic, 2007. ARITH '07. 18th IEEE Symposium on
Publication Date: 25-27 June 2007
On page(s): 205-216
Location: Montepellier,
ISSN: 1063-6889
ISBN: 0-7695-2854-6
INSPEC Accession Number: 9830545
Digital Object Identifier: 10.1109/ARITH.2007.25
Current Version Published: 2007-07-16
Abstract
Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the available precision. The resulting cyclic dependency in floating-point accumulation inhibits parallelization of the computation, including efficient use of pipelining. In practice, however, we observe that floating-point operations are "mostly" associative. This observation can be exploited to parallelize floating-point accumulation using a form of optimistic concurrency. In this scheme, we first compute an optimistic associative approximation to the sum and then relax the computation by iteratively propagating errors until the correct sum is obtained. We map this computation to a network of 16 statically-scheduled, pipelined, double-precision floating-point adders on the Virtex-4 LX160 (-12) device where each floating-point adder runs at 296 MHz and has a pipeline depth of 10. On this 16 PE design, we demonstrate an average speedup of 6times with randomly generated data and 3-7times with summations extracted from Conjugate Gradient benchmarks.
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