Hardware Support for Accelerating Data Movement in Server Platform
Li Zhao
Bhuyan, L.N.
Iyer, R.
Makineni, S.
Newell, D.
Syst. Technol. Lab, Intel Corp., Hillsboro, OR;
This paper appears in: Computers, IEEE Transactions on
Publication Date: June 2007
Volume: 56,
Issue: 6
On page(s): 740-753
ISSN: 0018-9340
INSPEC Accession Number: 9479420
Digital Object Identifier: 10.1109/TC.2007.1036
Current Version Published: 2007-04-30
Abstract
Data movement (memory copies) is a very common operation during network processing and application execution on servers. The performance of this operation is rather poor on today's microprocessors due to the following aspects: 1) Several long-latency memory accesses are involved because the source and/or the destination are typically in memory, 2) latency hiding techniques, such as out-of-order execution, hardware threading, and prefetching, are not very effective for bulk data movement, and 3) microprocessors move data at register (small) granularity. In this paper, we show this overhead of bulk data movement and propose the use of dedicated copy engines to minimize it. We present a detailed analysis of copy engine architectures along two dimensions: 1) on-die versus off-die and 2) synchronous versus asynchronous. These copy engine architectures are superior to traditional direct memory access (DMA) engines because they are tightly coupled to the core architecture and enable lower overhead communication and signaling. We describe the hardware support required to implement these copy engines and integrate them into server platforms. We perform a detailed case study to evaluate the performance of these copy engines. The evaluation is based on an execution-driven simulator, which was extended with detailed models of copy engines. Our simulation results show that copy engines are effective in reducing the bulk data movement overhead and, hence, hold significant promise for high-performance server platforms
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