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GraphStep: A System Architecture for Sparse-Graph Algorithms
deLorimier, M.
Kapre, N.
Mehta, N.
Rizzo, D.
Eslick, I.
Rubin, R.
Uribe, T.E.
Knight, T.F.
DeHon, A.
Dept. of Comput. Sci., California Inst. of Technol., Pasadena, CA;
This paper appears in: Field-Programmable Custom Computing Machines, 2006. FCCM '06. 14th Annual IEEE Symposium on
Publication Date: 24-26 April 2006
On page(s): 143-151
Location: Napa, CA,
ISBN: 0-7695-2661-6
INSPEC Accession Number: 9274750
Digital Object Identifier: 10.1109/FCCM.2006.45
Current Version Published: 2006-12-11
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Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The graph structures are large, and the applications need regular access to a large, data-dependent portion of the graph for each operation (e.g., the algorithm may need to walk the graph, visiting all nodes, or propagate changes through many nodes in the graph). On conventional microprocessors, the graph structures exceed on-chip cache capacities, making main-memory bandwidth and latency the key performance limiters. To avoid this "memory wall," we introduce a concurrent system architecture for sparse graph algorithms that places graph nodes in small distributed memories paired with specialized graph processing nodes interconnected by a lightweight network. This gives us a scalable way to map these applications so that they can exploit the high-bandwidth and low-latency capabilities of embedded memories (e.g., FPGA Block RAMs). On typical spreading-activation queries on the ConceptNet Knowledge Base, a sample application, this translates into an order of magnitude speedup per FPGA compared to a state-of-the-art Pentium processor
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