Analysis and Software Implementation of a Robust Synchronizing PLL Circuit Based on the pq Theory
Rolim, L.G.B.
da Costa, D.R.
Aredes, M.
Univ. Fed. do Rio de Janeiro;
This paper appears in: Industrial Electronics, IEEE Transactions on
Publication Date: Dec. 2006
Volume: 53,
Issue: 6
On page(s): 1919-1926
ISSN: 0278-0046
INSPEC Accession Number: 9201862
Digital Object Identifier: 10.1109/TIE.2006.885483
Current Version Published: 2006-11-30
Abstract
This paper presents the analysis and software implementation of a robust synchronizing circuit, i.e., phase-locked loop (PLL) circuit, designed for use in the controller of active power line conditioners. The basic problem consists of designing a PLL circuit that can track accurately and continuously the positive-sequence component at the fundamental frequency and its phase angle even when the system voltage of the bus, to which the active power line conditioner is connected, is distorted and/or unbalanced. The fundamentals of the PLL circuit are discussed. It is shown that the PLL can fail in tracking the system voltage during startup under some adverse conditions. Moreover, it is shown that oscillations caused by the presence of subharmonics can be very critical and can pull the stable point of operation synchronized to that subharmonic frequency. Oscillations at the reference input are also discussed, and the solution of this problem is presented. Finally, experimental and simulation results are shown and compared
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