Using simulation and satisfiability to compute flexibilities in Boolean networks
Mishchenko, A.
Zhang, J.S.
Sinha, S.
Burch, J.R.
Brayton, R.
Chrzanowska-Jeske, M.
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA;
Abstract
Simulation and Boolean satisfiability (SAT) checking are common techniques used in logic verification. This paper shows how simulation and satisfiability (S&S) can be tightly integrated to efficiently compute flexibilities in a multilevel Boolean network, including the following: 1) complete "don't cares" (CDCs); 2) sets of pairs of functions to be distinguished (SPFDs); and 3) sets of candidate nodes for resubstitution. These flexibilities can be used in network optimization to change the network structure while preserving its functionality. In the first two applications, simulation quickly enumerates most of the solutions while SAT detects the remaining solutions. In the last application, simulation efficiently filters out most of the infeasible solutions while SAT checks the remaining candidates. The experimental results confirm that the combination of simulation and SAT offers a computation engine that outperforms binary decision diagrams, which are traditionally used in such applications.
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