A floating-point FPGA-based self-tuning regulator
Salcic, Z.
Jiaying Cao
Sing Kiong Nguang
Dept. of Electr. & Comput. Eng., Univ. of Auckland, New Zealand;
This paper appears in: Industrial Electronics, IEEE Transactions on
Publication Date: April 2006
Volume: 53,
Issue: 2
On page(s): 693- 704
ISSN: 0278-0046
INSPEC Accession Number: 8875926
Digital Object Identifier: 10.1109/TIE.2006.871702
Current Version Published: 2006-04-03
Abstract
Recursive-least-square (RLS) algorithm is widely used in many areas with real-time implementation using digital signal processors. In this paper, the authors present a pure hardware implementation of a self-tuning regulator (STR) that uses a real-time RLS algorithm as the parameter estimator. The STR contains a controller design circuit and a controller circuit. Due to RLS computation-precision and dynamic-range requirements, the hardware implementation uses a floating-point format. The floating-point processing elements presented in this paper use parameterized design, where the number of exponents and mantissa bits can be changed as the data range and the accuracy of a specific application require. The strategies for overcoming the covariance matrix asymmetrical problem during the hardware computation and the covariance matrix resetting is introduced when the system is poorly exciting are presented. The design was verified with real-time experiments using a new testbed. The experiment results are presented.
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