Computing Signal Delay in General RC Networks by Tree/Link Partitioning
Chan, P.K.
Karplus, K.
Computer Engineering, University of California, Santa Cruz, Santa Cruz, CA;
This paper appears in: Design Automation, 1989. 26th Conference on
Publication Date: 25-29 June 1989
On page(s): 485- 490
ISSN: 0738-100X
ISBN: 0-89791-310-8
Current Version Published: 2006-02-06
Abstract
Most RC simulators only handle tree networks, not arbitrary networks. We present an algorithm for computing signal delays in general RC networks using the RC-tree computation as the primary operation. We partition a given network into a spanning tree and link branches. Then we compute the signal delay of the spanning tree, and update the signal delay as we incrementally add the links back to reconstruct the original network. If m is the number of link branches, this algorithm requires m(m+1)/2 updated and m+1 tree delay evaluations. all the tree delay evaluations involve computing signal delays with the same resistive spanning tree, but with different values for the capacitors.
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